ASIC Chip Design Lead

Overview

SigmaSense is developing state-of-the-art touch controller ASICs for its breakthrough touch technology. We are seeking an ASIC Design leader for our next-generation chips. Must have a strong background and recent hands-on experience with SOC design. Must have experience in chip design and verification methodologies, mixed-signal chip integration, DFT implementation, low power design, silicon debugging, proven leadership, and experience working with cross-functional engineers, including contractors.

Responsibilities

  • Play lead role in delivering ASICs over the full development cycle including tape out, validation and ATE testing.
  • Provide technical leadership and make technical decisions on ASIC front-end, back-end, and post-silicon activities.
  • Take responsibility for planning chip development and align execution with program management.
  • Utilize and enhance best practices for ASIC development and drive successful execution for on-time and first-time-right silicon delivery.
  • Take ownership of evaluating and selecting IPs, including foundation IPs, and make buy or build decisions.
  • Provide leadership in ASIC design methodologies and EDA tool selections.
  • Work with chip architect and cross-functional team members on chip definition including pinout and package selection.
  • Identify risks as well as risk mitigation strategies on chip projects.
  • Drive and coordinate ASIC PPA analysis, articulate design and implementation trade-offs and participate in chip definition.
  • Work with chip architect and verification lead to ensure chip is fully verified to ensure first-time silicon success.
  • Take responsibility for pre-silicon FPGA validation.
  • Work with software and systems teams to validate silicon and resolve any silicon issues.

Qualifications

  • Experience with embedded processor (ARM core, RISC-V, Tensilica, or others) based SOC design and knowledge in industry-standard interface IPs.
  • 15 years or more experience in SOC design and verification with 10 years as a chip lead.
  • Require a successful track record for executing and delivering ASICs for production.
  • Experience with designing and implementing low-power mixed signal SOCs.
  • Experience and knowledge in DSP design are highly desirable.
  • Strong background and experience with ASIC flows.
  • Has good communication skills and teamwork personality.
  • Must have a BS in EE or related, MS in EE preferred.