ASIC Verification Lead/Manager

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Overview

SigmaSense is developing state-of-the-art touch controller ASICs for its breakthrough touch technology. We are seeking an ASIC Verification leader to head up the verification team working on next-generation chips. Must have a strong background and recent hands-on experience with SOC verification. Must have expertise in modern verification methodologies, proven leadership, and the ability to guide and mentor a team of verification engineers, including contractors.

Responsibilities

  • Lead ASIC verification team, develop test plans, and ensure successful execution of the plans.
  • Deliver verification test benches and infrastructure to meet all the verification requirements for Sigma Sense mixed signal SOCs targeted at touch controllers and other IOT applications.
  • Deliver detailed test plans for verification of power-aware mixed signal design by working with design engineers and architects.
  • Create and enhance constrained-random verification environments using System Verilog and UVM.
  • Work with architect and system engineers to understand use cases and create SOC test code for execution on embedded processor models to verify design meets functional requirements.
  • Generate coverage reports to identify verification gaps and enhance tests to ensure the design complies with chip specs.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Develop and implement test plans for gate-level simulations and power simulations.
  • Maintain and enhance DV flow setup.
  • Support chip validation team and testing team for test vector generation and system bring-up. Work with the validation team to debug any silicon issues.

Qualifications

  • 15 years or more experience in SOC verification with at least 5 years leading/managing a verification team.
  • Has solid background and understanding of all DV concepts and methodologies including assertion, coverage, test bench structure, and flow setup.
  • Has hands-on experience in low-power verification methodology and UPF.
  • Has hands-on experience in constrained randomization, block level, and top-level FW-driven verification methods.
  • Has hands-on experience with embedded processor (ARM core, RISC-V, Tensilica, or others) based SOC verification.
  • Has experience with assembly language/C language/Verilog/System Verilog.
  • Knowledge and experience in verification of DSP modules in SOC are highly desirable.
  • Knowledge of methodologies and experience in verification of mixed-signal designs is highly desirable.
  • Has a good understanding of UVM verification environment and methodology.
  • Has good communication skills and teamwork personality.
  • Must have a BS in EE or related, MS in EE preferred.
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