SigmaSense inventions unleash a radical transformation of how digital systems sense and interact with the analog world. With the invention of measuring current direct-to-digital, SigmaSense delivers high-fidelity sensing brought into the digital domain, an industry first.
SigmaSense captures the data that is “lost in the noise” to better inform ML and AI systems for more efficient, higher performance outcomes. Come be part of our team as we change the world one touch at a time.
SigmaSense is seeking an experienced and proficient Senior Design for Testability (DFT) Engineer to join our top-tier engineering team in Austin, Texas. In this role, you will work on complex integrated circuit (IC) projects, designing and implementing robust DFT strategies. Your expertise will be critical to ensure the testability and manufacturability of our state-of-the-art touch sensor products.
- Design, develop and implement advanced DFT techniques, including but not limited to ATPG, Scan chains, Memory BIST, Logic BIST, Boundary Scan, and JTAG.
- Conduct detailed DFT DRC rule checking, and closely collaborate with design and verification teams for its closure.
- Work on ATPG pattern generation, simulation, and verification for Stuck-at, Transition, Path Delay, and ATPG coverage improvement.
- Conduct and lead debug activities for pattern failures on silicon and correlate failures with ATE.
- Interface with product engineering and test engineering teams for test pattern bring-up and validation on ATE platforms.
- Leverage scripting languages for automating DFT flow and pattern verification.
- Prepare technical reviews and provide presentations about test structure architectures and trade-offs to peers and management.
- Support silicon bring-up from a DFT perspective.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of relevant experience or Master’s/PhD degree with 5+ years of experience.
- Good knowledge of DFT architectures and methodologies such as Scan, ATPG, Memory BIST, Logic BIST, Boundary Scan, etc.
- Hands-on experience with EDA tools such as Synopsys DFT Compiler, Cadence Encounter Test, or Mentor Tessent.
- Familiarity with VHDL, Verilog, and SystemVerilog for design and verification.
- Proficiency in scripting languages such as Perl, Python, or Tcl.
- In-depth understanding of digital design, CMOS, and VLSI designs.
- Strong problem-solving, debugging skills, and experience with silicon debugging from a DFT perspective.
- PhD in Electrical Engineering, Computer Engineering, or related field.
- Experience in multi-clock domain designs and low-power designs with UPF.
- Proficiency with post-silicon validation, silicon debugging, and yield enhancement.
- Experience with semiconductor ATE platforms.